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FabCat Service

Enabling the electronics industry is a current strategic goal for Egypt and in particular for the Ministry of Communications and Information Technology (MCIT). As it is one of the mandates of TIEC and in view of the many MSEs requests received, a new TIEC service, called Fabrication Catalyst (FabCat) Service, is proposed to support growth in this industry. The service enables fabrication of electronic chips designed by Egyptian micro and small enterprises (MSEs) and by academic university projects. This program support the fabrication in either CMOS or MEMS technologies.

FabCat’s main offering principles are as follows:

  • Beneficiaries: Egyptian MSEs working in VLSI design and Egyptian Governmental Universities having electronics programs.


  • Price: Service price is rated per chip dimensions and technology.


  • Approach: Service is offered in annual calls (rounds); 2 calls for MSEs and one call for governmental universities.


  • Value: Customer uses the fabricated chips to validate and improve design.


  • Selection: Selection Committee composed of experts from industry and academia is formed .


  • IP Ownership: Applicant owns all IP rights to the submitted design.

Service Beneficiaries

The FabCat program is intended towards industry (MSEs) to increase the value of their products in the market and academia to validate their designs in order to enhance their research through the fabrication of their designs.    

1- MSEs

For MSEs, the fabrication of innovative designs is supported to provide MSEs a better opportunity to showcase their products to the market. The end impact is the growth of the MSE.

The below figure shows the benefits for MSEs.    


FabCat Service for MSEs.


2- Academia

For academic  university projects, the project advisor is encouraged to propose real-world industrial projects for students. This enhances match making between student capacity and industry needs and hence improves employment opportunities in local and MNCs working in the VLSI area.The service also motivates entrepreneurship through encouraging student with relevant designs to consider establishing their own business and applying for incubation programs such as those offered by TIEC. In addition, chances for student recognition through competitions. Such as TIEC’s IbTIECar (VLSI track) are increased. Last but not least, the FabCat service enhances generation of Egyptian research publications and IPs.

The below figure shows the benefits for academia.


FabCat Service Impact for University Projects.

FabCat Service Description


The FabCat service is announced in annual calls (rounds).In each round, TIEC announces the service for funding the fabrication of electronics design using CMOS/MEMS technologies for both Industry and Academia.  
Below, you will find the fabcat service process model..


bullet Industry:

In each round for industry, TIEC announces the service for funding the fabrication of electronics design uses CMOS/MEMS technologies for both Micro and Small Enterprises (MSEs) working in the VLSI area. The applicants from industry are asked to submit a proposal which will be evaluated against selection criteria. The winning applicants are announced, and asked to finalize the design, and submit fabrication file(s) to the fabrication organization, namely the foundry. Once the designs are fabricated, the foundry shall send the fabricated chips. The MSE will use the fabricated chip under supervision of TIEC to do the required measurement, and the chip will be finally kept in the innovation showroom in TIEC.

There are no limitations for the design model, while the GDS files should be submitted within one year.


bullet Academia:

In each round for academia, TIEC announces the service for funding the fabrication of electronics design using CMOS/MEMS technologies for academic university projects. The applicants from academia are asked to submit a proposal which will be evaluated against selection criteria. The winning applicants are announced, and asked to finalize the design, and submit fabrication file(s) which will be validated by TIEC and submitted to the fabrication organization, namely the foundry. Once the designs are fabricated, The foundry send the fabricated chips. The university project will use the fabricated chip under supervision of TIEC to do the required measurement, and the chip will be finally kept in the innovation showroom in TIEC.

Eligibility Criteria:


Industry Applicants:
Any applying company should satisfy the following conditions:

  1. 1- It should be in the category of MSE (Micro and Small Enterprises): Number of Employees should be not more than 50 employees.
  2. 2- It should be working in the field of Electronic Design and Development.
  3. 3- In case of multi-national companies, it should have design and development team residing in Egypt.
  4. 4- Only 1 application is permitted for each applicant.

Academia Applicants

  1. 1- The Professor supervising the proposed project should submit.
  2. 2- The service is available for governmental universities.
  3. 3- The service is provided to university projects in faculties of engineering , who belong to the departments of Electronics , Communication, Computer or Mechatronics Engineering.
  4. 4- Only 1 application is permitted for each applicant.

Selection Criteria shall cover the following Points:

MSEs Applications University Projects Applications
Design
  • Novelty
  • Number and type of applications where this chip might be used
  • Feasibility
  • Number of tiles (less number of tiles, higher score)
Company
  • Past work
  • Commercial registration date
  • Exports
  • Awards/Partnerships/Certificates
  • Patents/Publications
Design
  • Feasibility
  • Number and type of applications where this chip might be used
  • Number of tiles (less number of tiles, higher score)
Project Advisor
  • Patents/Publications

FAQs

Why this service is offered?

Many investments in VLSI design are in companies with no fabrication facilities namely fabless design companies. Although these companies only sell their design, silicon fabrication is important to validate the design through measurements which might lead to design changes. The electronics design which is validated on silicon gets high credibility than the design which is only simulated and this is reflected on sales of the design. Most MSEs in Egypt cannot afford the fabrication cost for a prototype which might exceed 200,000 LE for a 3 mm2 chip for technology 65 nm. This prevents companies from expanding their market and hence limits their growth. Moreover, undergraduate students rarely go through the process of tape-out when the design Is being prepared for fabrication. Addressing these issues in the electronics industry in Egypt and responding to requests from start-ups and MSEs working in this industry, TIEC developed the FabCat service to enable fabrication of VLSI chips.

Who are the members of the selection committee?

The selection committee is composed of experts from the industry and academia. There are two important issues in managing the committee members: the protection of the intellectual property of the applicant, and resolving conflict of interest between the members and the applicant.

What are the actions taken for IP Protection?
  • Selection committee member sign a Non-Disclosure Agreement (NDA)
  • The submitted proposal only includes the commercial information about the design that should be available to the public and does not include the implementation details
  • Submission of the final GDS file for MSEs will be done directly to the foundry. In case of university project, submission will be first processed by the technical support team to verify and integrate before sending it to the foundry for fabrication
How the Conflict of Interest for Judges is handled?
  • The proposal is forwarded to members as anonymous submissions
  • The selection committee members from the industry shall referee academia submissions (university projects) and vice versa
  • The selection commiittee members includes Egyptian members working abroad in the academia and industry



  • For more details please contact us on fabcat@tiec.gov.eg

August 2015




The 2015/2016 Round. 


Date

Event

20/9/2015

Announcement and Press Release

4/10/2015

Open Submission

25/10/2015

Close Submission

10/12/2015

Selection Committee Decision Received

24/12/2015

Final Decision and Winners Announcement

15/6/2016

Final GDS Submission

15/9/2016

Chips Received

December 2016

Closing Event

Submission Details

Submission is closed now.

Technical Notes:
  • The offered CMOS Technology is UMC L130 Mixed-Mode/RF - 1P8M2T - 1.2V/3.3V. The offered chip tile size is 1525 x 1525 um .
  • The offered MEMS Technology is MEMSCAP SOIMUMPs technology. The offered chip tile size is 4000 x 4000 um .
  • The TIEC technical support team will support University Projects during tapeout.

Important Note:

Once an applicant is selected to participate, the applicant is expected to sign the service agreement and pay the specified fees. Note that if the selected applicant didn't succeeded in submitting his GDS by the specified deadline, then he has actually wasted an opportunity that someone else could have benefited from. Accordingly, selected applicants who don't submit their GDS on time will be penalized by losing the fees they paid in addition to being banned from particpating in the program for 1 year. However, if the selected applicant gives TIEC a 1 month notice (before the GDS submission deadline) that he will not be able to submit, then he will be only penalized by losing 50% of the paid fees, and would still be banned from participating in the program for 1 year.


Any application that violates any of these rules will be filtered out.

For more details please contact us on fabcat@tiec.gov.eg


KPIs

Measuring Progress

# of Fabricated projects


August 2014 ( Academia )




The 2013/2014 Academic Round.


Date

Event

Aug 31, 2014

Announcement and Press Release

Sept 29, 2014

Open Submission

Nov 6, 2014

Close Submission

Nov 30, 2014

Selection Committee Decision Received

Dec 7, 2014

Final Decision and Winners Announcement

June 28, 2015

Final GDS Submission

Nov 15, 2015

Chips Received

Dec 20, 2015

Closing Event

Submission Details

The submission is closed now

Proposal Format:
The proposal will be in the form of a data sheet that includes:
  • Description of the circuit.
  • Architecture (block diagram).
  • Preliminary I/O on the bus level.
  • Typical application and the role of the chip in the system.
  • Basic features.
  • Test setup.

Please download the FabCat Datasheet Template. This template will be required to be edited and submitted as a pdf file in the submission form. 

Fabrication File Format:

The applicant submits a GDS file to the foundry.


For more details please contact us on fabcat@tiec.gov.eg


Technical Notes:
  • The offered CMOS Technology is UMC L130 Mixed-Mode/RF - 1P8M2T - 1.2V/3.3V. The offered chip tile size is 1525 x 1525 um .
  • The offered MEMS Technology is MEMSCAP SOIMUMPs technology. The offered chip tile size is 4000 x 4000 um .
  • The TIEC technical support team will support University Projects during tapeout.

Important Note:

Once an applicant is selected to participate, the applicant is expected to sign the service agreement and pay the specified fees. Note that if the selected applicant didn't succeeded in submitting his GDS by the specified deadline, then he has actually wasted an opportunity that someone else could have benefited from. Accordingly, selected applicants who don't submit their GDS on time will be penalized by losing the fees they paid in addition to being banned from particpating in the program for 1 year. However, if the selected applicant gives TIEC a 1 month notice (before the GDS submission deadline) that he will not be able to submit, then he will be only penalized by losing 50% of the paid fees, and would still be banned from participating in the program for 1 year.


Any application that violates any of these rules will be filtered out.

August 2014 ( Industry )




The 2014/2015 MSE August Round.


Date

Event

Aug 31, 2014

Announcement and Press Release

Sept 29, 2014

Open Submission

Oct 13, 2014

Close Submission

Oct 27, 2014

Judging Process Completed

Nov 10, 2014

Final Decision and Winners Announcement



Submission Details

The submission is closed now

Proposal Format:
The proposal will be in the form of a data sheet that includes:
  • Description of the circuit.
  • Architecture (block diagram).
  • Preliminary I/O on the bus level.
  • Typical application and the role of the chip in the system.
  • Basic features.
  • Test setup.

Please download the FabCat Datasheet Template. This template will be required to be edited and submitted as a pdf file in the submission form. 

Fabrication File Format:

The applicant submits a GDS file to the foundry.


For more details please contact us on fabcat@tiec.gov.eg



February 2014 ( Industry )




The 2014/2015 February MSE Round.


Date

Event

February 1 , 2014

Announcement and Press Release

February 27, 2014

Open Submission

March 13, 2014

Close Submission

March 27, 2014

Judging Process Completed

April 10, 2014

Final Decision and Winners Announcement



Submission Details

- Please Create an account , fill the application form and attach your datasheet (the FabCat Datasheet Template).

- The deadline for submitting industry proposals for February round is 11:59 pm ,March 13th 2014..

- If you already have an account in the current round

Proposal Format:
The proposal will be in the form of a data sheet that includes:
  • Description of the circuit.
  • Architecture (block diagram).
  • Preliminary I/O on the bus level.
  • Typical application and the role of the chip in the system.
  • Basic features.
  • Test setup.

Please download the FabCat Datasheet Template. This template will be required to be edited and submitted as a pdf file in the submission form. 

Fabrication File Format:

The applicant submits a GDS file to the foundry.


For more details please contact us on fabcat@tiec.gov.eg



August 2013 ( Academia )




The 2013/2014 Academic Round.


Date

Event

2013/2014 Academic Round

D1

Announcement and Press Release

Tue Aug 20, 2013

D2

Open Submission

Sun Sept 29, 2013

D3

Close Submission

Sun Oct 13, 2013

D4

Judging Process Completed

Sun Oct 27, 2013

D5

Final Decision and Winners Announcement

Sun Nov 10, 2013

D6

Final GDS Submission

Starting from June 29, 2014

D7

Chips Received

Starting from Sun October 6, 2014



August 2013 Accepted Proposal

The following designs are accepted:

Proposal Title

Design Type

Proposal Contact Person

Applicant Affiliation

Andalus-I DSP Chip (Toledo Architecture)

Digital

Amr Wassal

Cairo University

Micropower Energy Harvesting

Mixed Signal

Ahmed Nader Mohieldin

Cairo University

12-bit, 200MS/s Pipeline Analog to Digital Converter (ADC) using 0.13µm CMOS technology

Mixed Signal

Mohamed Aboudina

Cairo University

Low Power WiFi Blocks

Mixed Signal

Emad Hegazi

Ain Shams University

A Multi-Standard Serial-Link Receiver

Mixed Signal

Sameh Ibrahim

Ain Shams University

All-Digital Delay-Locked Loop

Digital

Serag Eldin ElSayed Habib.

Cairo University

Multi-band/Multi-Standard Receiver Front-End

Mixed Signal

Mohamed El-Nozahi

Ain Shams University

iCrypt

Digital

Eslam Yahya

Benha University

Envelope Tracking PA

Mixed Signal

Faisal Hussien

Cairo University

Ultra Low Power Spike Sorting Processor

Digital

Gamal Mahrous Attiya

Minoufia University

High-Speed SerDes Transceivers for On-Chip Networks

Digital

Maged Ghoneima

Ain Shams University

Design of a Low Power Full Duplex RF Front End Circuit for Implanted Biomedical Devices

Mixed Signal

El-Sayed A. M. Hasaneen

Aswan University


August 2013 ( Industry )




The 2013/2014 MSE Round.


Date

Event

2013/2014 Academic Round

D1

Announcement and Press Release

Tue Aug 20, 2013

D2

Open Submission

Sun Sept 29, 2013

D3

Close Submission

Sun Oct 13, 2013

D4

Judging Process Completed

Sun Oct 27, 2013

D5

Final Decision and Winners Announcement

Sun Nov 10, 2013

D6

Final GDS Submission

Starting from June 29, 2014

D7

Chips Received

Starting from Sun October 6, 2014

"Note: There are no applicants from industry in this round."

Winners

i. August 2015

Applicant AffiliationApplication Title
Benha UniversityAsynchronous Lightweight Cryptography Accelerator
Ain Shams University Compact MEMS Scanner for High-speed Light Beam Steering
Ain Shams University Finesse-Enhanced Optical Tunable Filter for Gas Sensing Applications
Cairo UniversityUltra Low Power Transceiver for loT applications in 0.13µm Standard CMOS process - Part 2
Helwan University A CMOS Biochip for neuronal activity monitoring and stimulation
Ain Shams University A 10-GB/S SERDES PHY FOR IoT APPLICATIONS
Ain Shams University High Performance GPU (HPGPU2)
E-JUSTNarrow Band PHY Transceiver for WBANs
Ain Shams University Multi-band/Multi-standard PLL and ADC
Cairo UniversityNeural Monitoring/Stimulating Interfacing Platform
Cairo UniversityUltra Low Power Transceiver for loT applications in 0.13µm Standard CMOS process - Part 1
Ain Shams University802.11p Digital Baseband Processor for V2V & V2X Communication
Cairo University28 Gb/s CMOS WIRELINE RECEIVER with DFE/CTLE

ii. August 2014 ( Academia )

Proposal NoApplicant AffiliationApplication Title
13U0104 Ain Shams UniversityHigh Performance GPU (HPGPU)
13U0162 Cairo University On-Chip Network (OCN) FPGA
13U0164 Ain Shams University An Energy-Harvesting IC Datasheet
13U0165 Benha UniversityHomomorphic Implementation of the Advanced Encryption Standard (AES)
13U0170 Ain Shams University Boost Converter for Energy Harvester Applications
13U0167 Ain Shams University MEMS-based Piezoelectric Vibration Energy Harvesters
13U0166 Cairo University 12-bit, 250MS/s Pipeline Analog to Digital Converter (ADC) using modified correlated level shifting (CLS) in 0.13µm CMOS technology
13U0171 Cairo University Novel High Efficiency Large Step-Down Conversion Ratio Buck Converter for High DC Current applications in 0.13mm Standard CMOS process
13U0161 Cairo University A 12-16GHz 130nm CMOS I/Q Down Converter

iii. August 2013 ( Academia )

Fabcat helped the following 9 teams in the fabrication process over the industrial level to increase the value of their research areas.

Proposal NoApplicant Affiliation Application TypeApplication Title
Aug13U0088Ain Shams UniversityMixed Signal Low power WiFi Blocks.
Aug13U00104Ain Shams UniversityDigital High-Speed SerDes Transceivers for On-Chip Networks
Aug13U0092Benha UniversityDigital iCrypt
Aug13U0059Cairo UniversityMixed Signal 12-bit, 200MS/s Pipeline Analog to Digital Converter (ADC) using 0.13µm CMOS technology
Aug13U0091Ain Shams UniversityMixed Signal Multi-band/Multi-Standard Receiver Front-End
Aug13U0090Cairo UniversityDigital All-digital Delay-locked Loop
Aug13U0089Ain Shams UniversityMixed Signal A MULTI-STANDARD SERIAL-LINK RECEIVER
Aug13U0058Cairo UniversityMixed Signal Micropower Energy Harvesting
Aug13U0094Cairo UniversityMixed Signal Envelope tracking PA

iv. August 2013 ( Industry )

Fabcat helped just one company [ ELManara for Electronics ] in the fabrication process over the industrial level to increase the value of their products in the market share.

icon Tip of the week
Wishing for Innovation isn’t Enough
Innovation is increasingly viewed as critical to sustaining a competitive advantage in the changing global marketplace.
Many people indicate that their innovation efforts are lacking. What gives?

Source :http://www.entrepreneur.com/article/228516
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